搜索资源列表
farrow
- 一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
CLOCK-ON-ALTERA-DEV-NOARD-RONTEX
- 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试. 文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等. 调试步骤就不讲了,管脚分配请网友自行完成. 开发板 Altera Cyclone II EP2C35F672C6 软件平台 Quartus II 语言 verilogHDL-These are all the project
processor
- The purpose of this project is to design a simple Processor Unit
A_digital_WaveformGenerator_and_Oscilloscope_based
- 一种基于BASYS开发板(Xilinx Spartan-3E FPGA)的波形发生器和示波器的设计，可以产生多种可调波形，并实时显示在电脑显示器或者投影仪上。波形发生器采用基于ROM的数字控制振荡器（NCO）实现，示波器采用VGA接口实时显示。-A kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.T
POTS.tar
- Pivoting Object Tracking System - This project implements an object recognition system, where a camera tracks the position of an object. The camera is mounted on an iRobot Create two-wheeled robot, which rotates according to the control signal
RVD.tar
- Realtime Video Display - Displaying real time video captured from a camera is an essential function in a vari- ety of applications ranging from CCTV se- curity monitoring to webconference meet- ings. In this project, we propose to build a s
shejishengjiangji
- 对电梯的基本功能进行了实现，并把电梯的一些特殊功能进行了改进，这是本人的毕业设计程序。-The basic functions of the elevator to achieve, and to lift some of the special features have been improved, this is my graduation project process.
fft
- vhdl code and verilog code for an 128 point fft processor which has to be executed in xlinx software as needed for course project
Thermometer
- thermometer vhdl project
Greedy_Snake_verilog
- 基于FPGA的verilog代码，在Spartan3开发板上实现了传统贪吃蛇的游戏，通过VGA显示在屏幕上。按键控制方向。-This is a FPGA project, which used verilog and implemented the traditional game of Greedy Snake.
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
TanSweeLing
- project mp3 decoder in hardware
a-vhdl-can-controller
- a vhdl can controller project using vhdl programmming language-a vhdl can controller project using vhdl programmming language..
all-digital-fm-receiver
- all digital fm receiver using vhdl programming language project for electronics and communication engineering students.
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
POC-Project
- 系统总线与打印机之间的借口：并行输出控制器POC的设计。涉及POC与CPU，POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.
A-VHDL-Primer---Bhasker
- VHDL exaples project from CPLD or FPGA
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
40716003-VHDL
- What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid